Constants, register addresses, masks, and defaults for the DRV8704 driver. More...

#include <stdint.h>
#include <SPI.h>

Include dependency graph for drv8704_defs.h:

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Macros
#define	DRV8704_ADDRESS_MASK 0x0007U

#define	DRV8704_ADDRESS_SHIFT 12U

#define	DRV8704_BLANK_DEFAULT 0x0080U

#define	DRV8704_BLANK_TBLANK_MASK 0x00FFU

#define	DRV8704_BLANK_TBLANK_SHIFT 0U

#define	DRV8704_CTRL_DEFAULT 0x0301U

#define	DRV8704_CTRL_DTIME_MASK 0x0C00U

#define	DRV8704_CTRL_DTIME_SHIFT 10U

#define	DRV8704_CTRL_ENBL_MASK 0x0001U

#define	DRV8704_CTRL_ENBL_SHIFT 0U

#define	DRV8704_CTRL_ISGAIN_MASK 0x0300U

#define	DRV8704_CTRL_ISGAIN_SHIFT 8U

#define	DRV8704_DECAY_DECMOD_MASK 0x0700U

#define	DRV8704_DECAY_DECMOD_SHIFT 8U

#define	DRV8704_DECAY_DEFAULT 0x0010U

#define	DRV8704_DECAY_TDECAY_MASK 0x00FFU

#define	DRV8704_DECAY_TDECAY_SHIFT 0U

#define	DRV8704_DEFAULT_INPUT_PWM_HZ 5000U

#define	DRV8704_DEFAULT_PWM_RES_BITS 10U

#define	DRV8704_DRIVE_DEFAULT 0x0FA5U

#define	DRV8704_DRIVE_IDRIVEN_MASK 0x0300U

#define	DRV8704_DRIVE_IDRIVEN_SHIFT 8U

#define	DRV8704_DRIVE_IDRIVEP_MASK 0x0C00U

#define	DRV8704_DRIVE_IDRIVEP_SHIFT 10U

#define	DRV8704_DRIVE_OCPDEG_MASK 0x000CU

#define	DRV8704_DRIVE_OCPDEG_SHIFT 2U

#define	DRV8704_DRIVE_OCPTH_MASK 0x0003U

#define	DRV8704_DRIVE_OCPTH_SHIFT 0U

#define	DRV8704_DRIVE_TDRIVEN_MASK 0x0030U

#define	DRV8704_DRIVE_TDRIVEN_SHIFT 4U

#define	DRV8704_DRIVE_TDRIVEP_MASK 0x00C0U

#define	DRV8704_DRIVE_TDRIVEP_SHIFT 6U

#define	DRV8704_MAX_INPUT_PWM_HZ 500000U

#define	DRV8704_MAX_PWM_RES_BITS 16U

#define	DRV8704_MIN_INPUT_PWM_HZ 100U

#define	DRV8704_OFF_DEFAULT 0x0130U

#define	DRV8704_OFF_PWMMODE_MASK 0x0100U

#define	DRV8704_OFF_PWMMODE_PWM 0x0100U

#define	DRV8704_OFF_PWMMODE_SHIFT 8U

#define	DRV8704_OFF_TOFF_MASK 0x00FFU

#define	DRV8704_OFF_TOFF_SHIFT 0U

#define	DRV8704_READ_BIT 0x8000U

#define	DRV8704_REG_BLANK 0x03U

#define	DRV8704_REG_CTRL 0x00U

#define	DRV8704_REG_DECAY 0x04U

#define	DRV8704_REG_DRIVE 0x06U

#define	DRV8704_REG_OFF 0x02U

#define	DRV8704_REG_RESERVED 0x05U

#define	DRV8704_REG_STATUS 0x07U

#define	DRV8704_REG_TORQUE 0x01U

#define	DRV8704_REGISTER_COUNT 8U

#define	DRV8704_REGISTER_MASK 0x0FFFU

#define	DRV8704_RESET_PULSE_WIDTH_US 10U

#define	DRV8704_RESET_RECOVERY_US 10U

#define	DRV8704_SPI_MODE SPI_MODE0

#define	DRV8704_SPI_ORDER MSBFIRST

#define	DRV8704_SPI_SPEED 1000000U

#define	DRV8704_STATUS_AOCP_MASK 0x0002U

#define	DRV8704_STATUS_AOCP_SHIFT 1U

#define	DRV8704_STATUS_APDF_MASK 0x0008U

#define	DRV8704_STATUS_APDF_SHIFT 3U

#define	DRV8704_STATUS_BOCP_MASK 0x0004U

#define	DRV8704_STATUS_BOCP_SHIFT 2U

#define	DRV8704_STATUS_BPDF_MASK 0x0010U

#define	DRV8704_STATUS_BPDF_SHIFT 4U

#define	DRV8704_STATUS_DEFAULT 0x0000U

#define	DRV8704_STATUS_FAULT_MASK 0x003FU

#define	DRV8704_STATUS_OTS_MASK 0x0001U

#define	DRV8704_STATUS_OTS_SHIFT 0U

#define	DRV8704_STATUS_UVLO_MASK 0x0020U

#define	DRV8704_STATUS_UVLO_SHIFT 5U

#define	DRV8704_TORQUE_DEFAULT 0x00FFU

#define	DRV8704_TORQUE_MASK 0x00FFU

#define	DRV8704_TORQUE_SHIFT 0U

#define	DRV8704_WAKE_DELAY_US 1000U

#define	DRV8704_WRITE_BIT 0x0000U

Detailed Description

Constants, register addresses, masks, and defaults for the DRV8704 driver.

Macro Definition Documentation

◆ DRV8704_ADDRESS_MASK

#define DRV8704_ADDRESS_MASK 0x0007U

◆ DRV8704_ADDRESS_SHIFT

#define DRV8704_ADDRESS_SHIFT 12U

◆ DRV8704_BLANK_DEFAULT

#define DRV8704_BLANK_DEFAULT 0x0080U

◆ DRV8704_BLANK_TBLANK_MASK

#define DRV8704_BLANK_TBLANK_MASK 0x00FFU

◆ DRV8704_BLANK_TBLANK_SHIFT

#define DRV8704_BLANK_TBLANK_SHIFT 0U

◆ DRV8704_CTRL_DEFAULT

#define DRV8704_CTRL_DEFAULT 0x0301U

◆ DRV8704_CTRL_DTIME_MASK

#define DRV8704_CTRL_DTIME_MASK 0x0C00U

◆ DRV8704_CTRL_DTIME_SHIFT

#define DRV8704_CTRL_DTIME_SHIFT 10U

◆ DRV8704_CTRL_ENBL_MASK

#define DRV8704_CTRL_ENBL_MASK 0x0001U

◆ DRV8704_CTRL_ENBL_SHIFT

#define DRV8704_CTRL_ENBL_SHIFT 0U

◆ DRV8704_CTRL_ISGAIN_MASK

#define DRV8704_CTRL_ISGAIN_MASK 0x0300U

◆ DRV8704_CTRL_ISGAIN_SHIFT

#define DRV8704_CTRL_ISGAIN_SHIFT 8U

◆ DRV8704_DECAY_DECMOD_MASK

#define DRV8704_DECAY_DECMOD_MASK 0x0700U

◆ DRV8704_DECAY_DECMOD_SHIFT

#define DRV8704_DECAY_DECMOD_SHIFT 8U

◆ DRV8704_DECAY_DEFAULT

#define DRV8704_DECAY_DEFAULT 0x0010U

◆ DRV8704_DECAY_TDECAY_MASK

#define DRV8704_DECAY_TDECAY_MASK 0x00FFU

◆ DRV8704_DECAY_TDECAY_SHIFT

#define DRV8704_DECAY_TDECAY_SHIFT 0U

◆ DRV8704_DEFAULT_INPUT_PWM_HZ

#define DRV8704_DEFAULT_INPUT_PWM_HZ 5000U

◆ DRV8704_DEFAULT_PWM_RES_BITS

#define DRV8704_DEFAULT_PWM_RES_BITS 10U

◆ DRV8704_DRIVE_DEFAULT

#define DRV8704_DRIVE_DEFAULT 0x0FA5U

◆ DRV8704_DRIVE_IDRIVEN_MASK

#define DRV8704_DRIVE_IDRIVEN_MASK 0x0300U

◆ DRV8704_DRIVE_IDRIVEN_SHIFT

#define DRV8704_DRIVE_IDRIVEN_SHIFT 8U

◆ DRV8704_DRIVE_IDRIVEP_MASK

#define DRV8704_DRIVE_IDRIVEP_MASK 0x0C00U

◆ DRV8704_DRIVE_IDRIVEP_SHIFT

#define DRV8704_DRIVE_IDRIVEP_SHIFT 10U

◆ DRV8704_DRIVE_OCPDEG_MASK

#define DRV8704_DRIVE_OCPDEG_MASK 0x000CU

◆ DRV8704_DRIVE_OCPDEG_SHIFT

#define DRV8704_DRIVE_OCPDEG_SHIFT 2U

◆ DRV8704_DRIVE_OCPTH_MASK

#define DRV8704_DRIVE_OCPTH_MASK 0x0003U

◆ DRV8704_DRIVE_OCPTH_SHIFT

#define DRV8704_DRIVE_OCPTH_SHIFT 0U

◆ DRV8704_DRIVE_TDRIVEN_MASK

#define DRV8704_DRIVE_TDRIVEN_MASK 0x0030U

◆ DRV8704_DRIVE_TDRIVEN_SHIFT

#define DRV8704_DRIVE_TDRIVEN_SHIFT 4U

◆ DRV8704_DRIVE_TDRIVEP_MASK

#define DRV8704_DRIVE_TDRIVEP_MASK 0x00C0U

◆ DRV8704_DRIVE_TDRIVEP_SHIFT

#define DRV8704_DRIVE_TDRIVEP_SHIFT 6U

◆ DRV8704_MAX_INPUT_PWM_HZ

#define DRV8704_MAX_INPUT_PWM_HZ 500000U

◆ DRV8704_MAX_PWM_RES_BITS

#define DRV8704_MAX_PWM_RES_BITS 16U

◆ DRV8704_MIN_INPUT_PWM_HZ

#define DRV8704_MIN_INPUT_PWM_HZ 100U

◆ DRV8704_OFF_DEFAULT

#define DRV8704_OFF_DEFAULT 0x0130U

◆ DRV8704_OFF_PWMMODE_MASK

#define DRV8704_OFF_PWMMODE_MASK 0x0100U

◆ DRV8704_OFF_PWMMODE_PWM

#define DRV8704_OFF_PWMMODE_PWM 0x0100U

◆ DRV8704_OFF_PWMMODE_SHIFT

#define DRV8704_OFF_PWMMODE_SHIFT 8U

◆ DRV8704_OFF_TOFF_MASK

#define DRV8704_OFF_TOFF_MASK 0x00FFU

◆ DRV8704_OFF_TOFF_SHIFT

#define DRV8704_OFF_TOFF_SHIFT 0U

◆ DRV8704_READ_BIT

#define DRV8704_READ_BIT 0x8000U

◆ DRV8704_REG_BLANK

#define DRV8704_REG_BLANK 0x03U

◆ DRV8704_REG_CTRL

#define DRV8704_REG_CTRL 0x00U

◆ DRV8704_REG_DECAY

#define DRV8704_REG_DECAY 0x04U

◆ DRV8704_REG_DRIVE

#define DRV8704_REG_DRIVE 0x06U

◆ DRV8704_REG_OFF

#define DRV8704_REG_OFF 0x02U

◆ DRV8704_REG_RESERVED

#define DRV8704_REG_RESERVED 0x05U

◆ DRV8704_REG_STATUS

#define DRV8704_REG_STATUS 0x07U

◆ DRV8704_REG_TORQUE

#define DRV8704_REG_TORQUE 0x01U

◆ DRV8704_REGISTER_COUNT

#define DRV8704_REGISTER_COUNT 8U

◆ DRV8704_REGISTER_MASK

#define DRV8704_REGISTER_MASK 0x0FFFU

◆ DRV8704_RESET_PULSE_WIDTH_US

#define DRV8704_RESET_PULSE_WIDTH_US 10U

◆ DRV8704_RESET_RECOVERY_US

#define DRV8704_RESET_RECOVERY_US 10U

◆ DRV8704_SPI_MODE

#define DRV8704_SPI_MODE SPI_MODE0

◆ DRV8704_SPI_ORDER

#define DRV8704_SPI_ORDER MSBFIRST

◆ DRV8704_SPI_SPEED

#define DRV8704_SPI_SPEED 1000000U

◆ DRV8704_STATUS_AOCP_MASK

#define DRV8704_STATUS_AOCP_MASK 0x0002U

◆ DRV8704_STATUS_AOCP_SHIFT

#define DRV8704_STATUS_AOCP_SHIFT 1U

◆ DRV8704_STATUS_APDF_MASK

#define DRV8704_STATUS_APDF_MASK 0x0008U

◆ DRV8704_STATUS_APDF_SHIFT

#define DRV8704_STATUS_APDF_SHIFT 3U

◆ DRV8704_STATUS_BOCP_MASK

#define DRV8704_STATUS_BOCP_MASK 0x0004U

◆ DRV8704_STATUS_BOCP_SHIFT

#define DRV8704_STATUS_BOCP_SHIFT 2U

◆ DRV8704_STATUS_BPDF_MASK

#define DRV8704_STATUS_BPDF_MASK 0x0010U

◆ DRV8704_STATUS_BPDF_SHIFT

#define DRV8704_STATUS_BPDF_SHIFT 4U

◆ DRV8704_STATUS_DEFAULT

#define DRV8704_STATUS_DEFAULT 0x0000U

◆ DRV8704_STATUS_FAULT_MASK

#define DRV8704_STATUS_FAULT_MASK 0x003FU

◆ DRV8704_STATUS_OTS_MASK

#define DRV8704_STATUS_OTS_MASK 0x0001U

◆ DRV8704_STATUS_OTS_SHIFT

#define DRV8704_STATUS_OTS_SHIFT 0U

◆ DRV8704_STATUS_UVLO_MASK

#define DRV8704_STATUS_UVLO_MASK 0x0020U

◆ DRV8704_STATUS_UVLO_SHIFT

#define DRV8704_STATUS_UVLO_SHIFT 5U

◆ DRV8704_TORQUE_DEFAULT

#define DRV8704_TORQUE_DEFAULT 0x00FFU

◆ DRV8704_TORQUE_MASK

#define DRV8704_TORQUE_MASK 0x00FFU

◆ DRV8704_TORQUE_SHIFT

#define DRV8704_TORQUE_SHIFT 0U

◆ DRV8704_WAKE_DELAY_US

#define DRV8704_WAKE_DELAY_US 1000U

◆ DRV8704_WRITE_BIT

#define DRV8704_WRITE_BIT 0x0000U

Macros